Ponente
Descripción
Real-time event reconstruction at the HL-LHC demands machine-learning algorithms that fit strict FPGA latency, resource, and throughput budgets, motivating a co-design between model architecture and firmware implementation. We present an FPGA-aware Graph Neural Network targeting the CMS Overlap Muon Track Finder (OMTF), exploring quantisation schemes from float32 down to INT8-PO2 together with fixed-size graph representations and latency-driven structural choices on AMD/Xilinx platforms. To make these designs reproducible and integration-ready, we introduce ARC, a plugin-agnostic, contract-driven framework that generates DUTs from interface YAMLs, orchestrates HLS, and provides a reusable verification runtime shared across algorithm variants. The combined flow shows that ML exploration and rigorous interface verification can co-evolve, replacing fragile ad-hoc testbenches with regression-friendly, contract-bound artefacts. Resulting GNN configurations meet L1-trigger-compatible resource and latency budgets, charting a viable path toward ML-based track-finding in the CMS Phase-2 trigger system.